1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a buffer circuit and a memory system which select a data strobe signal to output according to a number of data bits.
2. Description of the Related Art
In general, data applied to a memory array are synchronized with a data strobe signal.
FIG. 1 is a block diagram illustrating a process in which data to be applied to a memory array are synchronized with a data strobe signal.
A data strobe signal is generally used to process data in units of bytes. Thus, to process data DATA of 16 bits, a 16-bit data strobe signal is divided into two 8-bit signals. One signal is an upper data strobe signal UDQS, and the other signal is a lower data strobe signal LDQS.
When 16-bit data DATA is input, the upper data strobe signal UDQS latches an input of [8:15] data DATA, and the lower data strobe signal LDQS latches an input of [0:7] data DATA.
When 16 bits of data DATA are input, the upper data strobe signal UDQS buffered by a first input buffer 110 is applied as an upper latch data strobe signal PUDQS to a latch unit 140 through a switching unit 130.
The lower data strobe signal LDQS buffered by a second input buffer 120 is applied as a lower latch data strobe signal PLDQS to the latch unit 140 through the switching unit 130. The data DATA are synchronized with the upper and lower data strobe signals UDQS and LDQS and are applied to a memory array.
However, when 8 bits of data DATA are input, the input 8 data are latched using 8 data strobe signals among 16 data strobe signals by a bonding option.
Here, the upper data strobe signal UDQS, instead of the lower data strobe signal LDQS which is used as a reference signal for latching the 16 bits of data, generates the lower latch data strobe signal PLDQS through the switching unit 130.
That is to say, when 16 bits of data are processed, the upper data strobe signal UDQS applies the upper latch data strobe signal PUDQS to the latch unit 140 and the lower data strobe signal LDQS applies the lower latch data strobe signal PLDQS to the latch unit 140. The input 16 bits of data DATA to be applied to the memory array are synchronized with the upper latch data strobe signal PUDQS and the lower latch data strobe signal PLDQS.
However, when 8 bits of data are processed, the upper data strobe signal UDQS applies the upper latch data strobe signal PUDQS to the latch unit 140, and also applies the lower latch data strobe signal PLDQS to the latch unit 140. The upper latch data strobe signal PUDQS and the lower latch data strobe signal PLDQS are used as synchronizing signals of data DATA which are only input in units of 4 bits.
In more detail, when the processed data DATA are 16 bits, a control signal CTRL input to the switching unit 130 is set to a first level, whereas when the processed data DATA are 8 bits, it is set to a second level.
Thus, when the control signal CTRL is set to a first level, the switching unit 130 allows the upper data strobe signal UDQS to generate the upper latch data strobe signal PUDQS, and allows the lower data strobe signal LDQS to generate the lower latch data strobe signal PLDQS.
However, when the control signal CTRL is set to a second level, the switching unit 130 allows the upper data strobe signal UDQS to generate both the upper latch data strobe signal PUDQS and the lower latch data strobe signal PLDQS.
Such an operation is performed when the input data DATA are 4 bits as well. That is, except the case where the input data DATa are 16 bits, the upper data strobe signal UDQS generates both the upper latch data strobe signal PUDQS and the lower latch data strobe signal PLDQS.
FIG. 2 is a block diagram of the switching unit shown in FIG. 1.
Referring to FIG. 2, the switching unit 130 includes a first switch 210 which outputs the signal TUDQS obtained by buffering the upper data strobe signal UDQS by means of the first input buffer 110, a second switch 220 which outputs the buffered signal TUDQS as the lower latch data strobe signal PLDQS in response to an inverted control signal BCTRL, and a third switch 230 which receives the signal TLDQS obtained by buffering the lower data strobe signal LDQS by means of the second input buffer 120.
When the received control signal CTRL is set to a first level and the received inverted control signal BCTRL is set to a second level, it means that the input data DATA are 16 bits. Therefore, the second switch 220 is turned off and the third switch 230 is turned on.
Accordingly, the signal TUDQS obtained by buffering the upper data strobe signal UDQS by means of the first input buffer 110 is output as the upper latch data strobe signal PUDQS, and the signal TLDQS obtained by buffering the lower data strobe signal LDQS by means of the second input buffer unit 120 is output as the lower latch data strobe signal PLDQS.
When the received control signal CTRL is set to a second level and the received inverted control signal BCTRL is set to a first level, it means that the input data DATA are 8 bits or 4 bits. Therefore, the second switch 220 is turned on and the third switch 230 is turned off.
Accordingly, the signal TUDQS obtained by buffering the upper data strobe signal UDQS by means of the first input buffer 110 is output as the upper latch data strobe signal PUDQS and the lower latch data strobe signal PLDQS.
As mentioned, the upper latch data strobe signal PUDQS and the lower latch data strobe signal PLDQS are reference signals for latching the data DATA. When they are generated, if a separate switching circuit is added as shown in FIG. 1, speed is reduced and generation of the latched data DATA is delayed.
Further, since generation of the latched data DATA is delayed, the amount of time required for the data DATA to be transferred to the memory array is also increased. As a result, write time is reduced and skew of the data strobe signal caused by the switching unit 130 increases, thereby lengthening a setup/hold time of the data DATA.